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Computer Engineering Final Year Topic: Design and Evaluation of RISC Instruction Decoder Design

This Computer Engineering final year project investigates decoding a restricted instruction subset with unambiguous illegal-operation handling, linking hardware behaviour and software assumptions through an explicitly bounded prototype or simulation.

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Why choose this project topic?

The topic makes decoding a restricted instruction subset with unambiguous illegal-operation handling a testable computer-engineering problem with visible interfaces and failure cases. Measuring decode correctness, logic utilisation and invalid-opcode coverage helps a student compare design alternatives and explain how resource constraints affect the proposed implementation.

How do the selected hardware or embedded-software choices affect decode correctness, logic utilisation and invalid-opcode coverage when decoding a restricted instruction subset with unambiguous illegal-operation handling?

Choose an available development board or simulator, agree the supported interface and workload, and narrow decoding a restricted instruction subset with unambiguous illegal-operation handling with your supervisor.

Proposed project objectives

  1. 01Specify the interfaces, operating assumptions and expected behaviour for decoding a restricted instruction subset with unambiguous illegal-operation handling.
  2. 02Specify a small instruction set, implement an HDL decoder and compare outputs with an independent reference interpreter across generated encodings.
  3. 03Measure decode correctness, logic utilisation and invalid-opcode coverage and document failures, resource limits and reproducibility.

A suggested research approach

Specify a small instruction set, implement an HDL decoder and compare outputs with an independent reference interpreter across generated encodings. Keep all tests on owned, simulated or approved low-voltage equipment. Record hardware and tool versions, compare output with an independent reference, and evaluate decode correctness, logic utilisation and invalid-opcode coverage using normal, boundary and interrupted-operation cases.

What you will need

  • HDL development tools
  • Instruction specification
  • Reference decoder tests

Keep your project scope clear

The bounded core is not a complete commercial processor or a production-ready design. Project writing does not supply working firmware or manufactured hardware.

Computer Engineering project chapter outline

Use this outline as a starting point. You can edit the chapter titles to match your department’s format during setup.

  1. Chapter 1Introduction
  2. Chapter 2Literature Review
  3. Chapter 3System Analysis and Design
  4. Chapter 4System Implementation and Testing
  5. Chapter 5Summary, Conclusion and Recommendations

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