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Computer Engineering Final Year Topic: Design and Evaluation of FPGA Memory Test Controller

This Computer Engineering final year project investigates detecting simulated memory faults using bounded test sequences, linking hardware behaviour and software assumptions through an explicitly bounded prototype or simulation.

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Why choose this project topic?

The topic makes detecting simulated memory faults using bounded test sequences a testable computer-engineering problem with visible interfaces and failure cases. Measuring fault coverage, test cycles and controller resources helps a student compare design alternatives and explain how resource constraints affect the proposed implementation.

How do the selected hardware or embedded-software choices affect fault coverage, test cycles and controller resources when detecting simulated memory faults using bounded test sequences?

Choose an available development board or simulator, agree the supported interface and workload, and narrow detecting simulated memory faults using bounded test sequences with your supervisor.

Proposed project objectives

  1. 01Specify the interfaces, operating assumptions and expected behaviour for detecting simulated memory faults using bounded test sequences.
  2. 02Implement a memory-test controller, inject stuck and coupling faults in an HDL model and compare coverage with a simple write-read pattern.
  3. 03Measure fault coverage, test cycles and controller resources and document failures, resource limits and reproducibility.

A suggested research approach

Implement a memory-test controller, inject stuck and coupling faults in an HDL model and compare coverage with a simple write-read pattern. Keep all tests on owned, simulated or approved low-voltage equipment. Record hardware and tool versions, compare output with an independent reference, and evaluate fault coverage, test cycles and controller resources using normal, boundary and interrupted-operation cases.

What you will need

  • HDL memory model
  • Fault injection testbench
  • Reference test patterns

Keep your project scope clear

Simulation coverage does not certify physical memory or detect every manufacturing defect. Project writing does not supply working firmware or manufactured hardware.

Computer Engineering project chapter outline

Use this outline as a starting point. You can edit the chapter titles to match your department’s format during setup.

  1. Chapter 1Introduction
  2. Chapter 2Literature Review
  3. Chapter 3System Analysis and Design
  4. Chapter 4System Implementation and Testing
  5. Chapter 5Summary, Conclusion and Recommendations

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