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Computer Engineering Final Year Topic: Design and Evaluation of CAN Message Scheduling Simulation

This Computer Engineering final year project investigates analysing bounded message delay on a fictional shared controller network, linking hardware behaviour and software assumptions through an explicitly bounded prototype or simulation.

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Why choose this project topic?

The topic makes analysing bounded message delay on a fictional shared controller network a testable computer-engineering problem with visible interfaces and failure cases. Measuring worst-case delay, missed deadlines and bus utilisation helps a student compare design alternatives and explain how resource constraints affect the proposed implementation.

How do the selected hardware or embedded-software choices affect worst-case delay, missed deadlines and bus utilisation when analysing bounded message delay on a fictional shared controller network?

Choose an available development board or simulator, agree the supported interface and workload, and narrow analysing bounded message delay on a fictional shared controller network with your supervisor.

Proposed project objectives

  1. 01Specify the interfaces, operating assumptions and expected behaviour for analysing bounded message delay on a fictional shared controller network.
  2. 02Simulate arbitration with synthetic frames, compare identifier priorities and test bursts and retransmission assumptions.
  3. 03Measure worst-case delay, missed deadlines and bus utilisation and document failures, resource limits and reproducibility.

A suggested research approach

Simulate arbitration with synthetic frames, compare identifier priorities and test bursts and retransmission assumptions. Keep all tests on owned, simulated or approved low-voltage equipment. Record hardware and tool versions, compare output with an independent reference, and evaluate worst-case delay, missed deadlines and bus utilisation using normal, boundary and interrupted-operation cases.

What you will need

  • CAN scheduling simulator
  • Synthetic message set
  • Documented timing assumptions

Keep your project scope clear

Do not connect experimental messages to a real vehicle or claim functional-safety compliance. Project writing does not supply working firmware or manufactured hardware.

Computer Engineering project chapter outline

Use this outline as a starting point. You can edit the chapter titles to match your department’s format during setup.

  1. Chapter 1Introduction
  2. Chapter 2Literature Review
  3. Chapter 3System Analysis and Design
  4. Chapter 4System Implementation and Testing
  5. Chapter 5Summary, Conclusion and Recommendations

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