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Computer Engineering Final Year Topic: Design and Evaluation of FPGA Finite-State Machine Encoding

This Computer Engineering final year project investigates comparing circuit costs of alternative encodings for the same control logic, linking hardware behaviour and software assumptions through an explicitly bounded prototype or simulation.

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Why choose this project topic?

The topic makes comparing circuit costs of alternative encodings for the same control logic a testable computer-engineering problem with visible interfaces and failure cases. Measuring logic utilisation, timing estimate and fault-state handling helps a student compare design alternatives and explain how resource constraints affect the proposed implementation.

How do the selected hardware or embedded-software choices affect logic utilisation, timing estimate and fault-state handling when comparing circuit costs of alternative encodings for the same control logic?

Choose an available development board or simulator, agree the supported interface and workload, and narrow comparing circuit costs of alternative encodings for the same control logic with your supervisor.

Proposed project objectives

  1. 01Specify the interfaces, operating assumptions and expected behaviour for comparing circuit costs of alternative encodings for the same control logic.
  2. 02Implement equivalent binary and one-hot models, verify transitions and compare synthesis estimates under identical constraints.
  3. 03Measure logic utilisation, timing estimate and fault-state handling and document failures, resource limits and reproducibility.

A suggested research approach

Implement equivalent binary and one-hot models, verify transitions and compare synthesis estimates under identical constraints. Keep all tests on owned, simulated or approved low-voltage equipment. Record hardware and tool versions, compare output with an independent reference, and evaluate logic utilisation, timing estimate and fault-state handling using normal, boundary and interrupted-operation cases.

What you will need

  • HDL tools
  • Shared state-transition specification
  • Equivalence testbench

Keep your project scope clear

Synthesis estimates are tool- and target-dependent and do not establish fault tolerance by themselves. Project writing does not supply working firmware or manufactured hardware.

Computer Engineering project chapter outline

Use this outline as a starting point. You can edit the chapter titles to match your department’s format during setup.

  1. Chapter 1Introduction
  2. Chapter 2Literature Review
  3. Chapter 3System Analysis and Design
  4. Chapter 4System Implementation and Testing
  5. Chapter 5Summary, Conclusion and Recommendations

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