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Computer Engineering Final Year Topic: Design and Evaluation of FPGA Bus Arbitration Fairness

This Computer Engineering final year project investigates sharing a simulated bus among competing requesters without indefinite starvation, linking hardware behaviour and software assumptions through an explicitly bounded prototype or simulation.

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Why choose this project topic?

The topic makes sharing a simulated bus among competing requesters without indefinite starvation a testable computer-engineering problem with visible interfaces and failure cases. Measuring waiting cycles, starvation cases and logic cost helps a student compare design alternatives and explain how resource constraints affect the proposed implementation.

How do the selected hardware or embedded-software choices affect waiting cycles, starvation cases and logic cost when sharing a simulated bus among competing requesters without indefinite starvation?

Choose an available development board or simulator, agree the supported interface and workload, and narrow sharing a simulated bus among competing requesters without indefinite starvation with your supervisor.

Proposed project objectives

  1. 01Specify the interfaces, operating assumptions and expected behaviour for sharing a simulated bus among competing requesters without indefinite starvation.
  2. 02Implement fixed and rotating priority arbiters, replay bounded request patterns and formally or exhaustively check stated liveness conditions.
  3. 03Measure waiting cycles, starvation cases and logic cost and document failures, resource limits and reproducibility.

A suggested research approach

Implement fixed and rotating priority arbiters, replay bounded request patterns and formally or exhaustively check stated liveness conditions. Keep all tests on owned, simulated or approved low-voltage equipment. Record hardware and tool versions, compare output with an independent reference, and evaluate waiting cycles, starvation cases and logic cost using normal, boundary and interrupted-operation cases.

What you will need

  • HDL simulator
  • Synthetic request traces
  • Arbitration property specification

Keep your project scope clear

Bounded verification does not prove correctness for every unmodelled interface behaviour. Project writing does not supply working firmware or manufactured hardware.

Computer Engineering project chapter outline

Use this outline as a starting point. You can edit the chapter titles to match your department’s format during setup.

  1. Chapter 1Introduction
  2. Chapter 2Literature Review
  3. Chapter 3System Analysis and Design
  4. Chapter 4System Implementation and Testing
  5. Chapter 5Summary, Conclusion and Recommendations

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